SST201 [Linear Systems]
HIGH GAIN N-CHANNEL JFET; 高增益N沟道JFET型号: | SST201 |
厂家: | Linear Systems |
描述: | HIGH GAIN N-CHANNEL JFET |
文件: | 总2页 (文件大小:192K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
J/SST201 SERIES
HIGH GAIN
Linear Integrated Systems
N-CHANNEL JFET
FEATURES
DIRECT REPLACEMENT FOR SILICONIX J/SST201 SERIES
LOW CUTOFF VOLTAGE
HIGH GAIN
VGS(off) ≤ 1.5V
AV = 80 V/V
ABSOLUTE MAXIMUM RATINGS1
@ 25 °C (unless otherwise stated)
Maximum Temperatures
Storage Temperature
J SERIES
TO-92
SST SERIES
SOT-23
TOP VIEW
BOTTOM VIEW
-65 to +150 °C
-55 to +135 °C
1
D
S
Operating Junction Temperature
Maximum Power Dissipation
Continuous Power Dissipation
Maximum Current
3
G
D S G
2
1
2 3
350mW
50mA
Forward Gate Current
Maximum Voltages
Gate to Drain Voltage
Gate to Source Voltage
-40V
-40V
ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)
SYMBOL
CHARACTERISTIC
MIN TYP MAX UNITS CONDITIONS
J/SST201, 202 -40
Gate to Source
BVGSS
IG = -1µA, VDS = 0V
Breakdown Voltage
J/SST204
J/SST201
J/SST202
J/SST204
J/SST201
J/SST202
J/SST204
-25
-0.3
-0.8
-0.3
0.2
0.9
0.2
-2
V
-1.5
-4
2
1
4.5
3
Gate to Source Cutoff
Voltage
VGS(off)
VDS = 15V, ID = 10nA
Drain to Source
IDSS
mA
pA
VDS = 15V, VGS = 0V
Saturation Current2
IGSS
IG
ID(off)
Gate Reverse Current
Gate Operating Current
Drain Cutoff Current
-100
VGS = -20V, VDS = 0V
VDG = 10V, ID = 0.1mA
VDS = 15V, VGS = -5V
-2
2
J/SST201, 204 0.5
J/SST202
Forward
gfs
mS
pF
V
DS = 15V, VGS = 0V, f = 1kHz
DS = 15V, VGS = 0V, f = 1MHz
Transconductance
1
Ciss
Crss
en
Input Capacitance
4.5
1.3
6
V
Reverse Transfer Capacitance
Noise Voltage
nV/√Hz VDS = 10V, VGS = 0V, f = 1kHz
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
SOT-23
TO-92
0.89
1.03
0.175
0.195
0.130
0.155
0.37
0.51
1
3
2
0.045
0.060
1.78
2.05
2.80
3.04
LS XXX
YYWW
0.170
0.195
1.20
1.40
0.89
1.12
2.10
2.64
0.014
0.020
0.016
0.022
0.085
0.180
0.500
0.610
0.013
0.100
0.55
DIMENSIONS IN
MILLIMETERS
1
2
3
0.095
0.105
0.045
0.055
DIMENSIONS
IN INCHES.
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.
2. Pulse Test: PW ≤ 300µs, Duty Cycle ≤ 3%
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
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